The present invention is directed toward the field of multi-beam communication satellites that incorporate on-board digital processors. In particular, an analog pre-processor is disclosed for use with such digital satellites. The analog preprocessor is connected between the satellite""s receive circuitry and the on-board digital processor(s) in order to optimize the processing capability of the satellite, and to provide the ability to manage the risk of selecting a particular digital processor technology.
Communication satellites generally consist of a payload and a bus. The bus includes the satellite structure (or platform), electrical power system, thermal control system, propulsion system, and orbit control system. The payload, which is the communications part of the satellite, generally includes the antenna (receive and transmit) subsystem, the repeater, and a telemetry, tracking and command module. The present invention relates to improvements in the communications satellite payload, in particular the repeater section of a digital satellite.
A transparent repeater, also known as a xe2x80x9cbent pipexe2x80x9d repeater, performs filtering, frequency and power conversion, and switching between beams without altering the baseband signal in any manner. For large bandwidth carriers (i.e. commercial communications satellites), this filtering and switching is performed by analog means. For smaller bandwidth carriers it is possible to perform some of the repeater functions digitally, such as the filtering and switching steps.
As distinguished from the transparent repeater, a regenerative repeater processes the baseband signal content of the RF uplink signal such that the individual carrier signals of an uplink beam are demodulated (i.e. the information bits of the signal are recovered). A regenerative repeater can also switch the demodulated data to an arbitrary output beam and time multiplex (as in a TDM system) the switched signals from all beams on to one or a few downlink carriers using an optimized remodulation and/or multiple access scheme, thus resulting in a more efficient system. Transparent repeaters are generally (but not always) analog systems, whereas regenerative repeaters generally employ on-board digital processors. For a basic discussion of communication satellite design considerations see M. Richharia, Satellite Communication Systemsxe2x80x94Design Principles, McGraw-Hill, 1995.
Recently proposed commercial satellite systems for use in the Ka-band spectrum (20/30 GHz) include multi-beam architectures with as many as 192 beams and on-board digital processing technology. The amount of frequency spectrum (i.e. bandwidth) in each uplink beam to be digitized and processed by the on-board digital processor(s) is typically in the range of 125 MHz, but could be much larger. The resultant bandwidth that must be processed digitally on such satellites presents a serious design problem.
There is a need to design an architecture that can handle this bandwidth, while minimizing the risk, power, and size of the satellite repeater, and hence the overall satellite architecture. The risk associated with selecting a particular digital processor is determined by the bandwidth to be processed. For example, a lower power processor capable of processing 25 MHz of bandwidth that incorporates standard space-qualified hardware is much less risky to employ than a higher power 200 MHz processor that may include components and elements that have not been previously proven in space.
In FIG. 1, a prior art digital satellite repeater is shown, having one-to-one correspondence between uplink beams and digital processors. In this figure, each uplink beam (1-N) is shown connected to an individual receive element 10 of an antenna. As described below in the detailed description, multiple uplink beams could be connected to each receive element 10 in a process known as beamforming.
A receiver 12 is connected to the receive element 10 and receives signals covering a certain bandwidth of a given beam from an associated antenna by filtering the desired bandwidth to remove unwanted out-of-band signals and noise, and downconverting to a common intermediate frequency for all beams. This entire bandwidth is routed to mixer 16, where the received RF signal is downconverted to a baseband signal by mixing with a fixed signal from a local oscillator 14. The baseband signal is filtered by an Image Rejection Filter (IRF) 18, which is a low pass filter that eliminates the higher frequency image that is a byproduct of the frequency downconversion process. All of the carrier signals that comprise the beam are routed to one of N digital processors 20 which perform analog to digital conversion and other digital processing, such as demodulation, switching, etc.
The well-known elements of the repeater that are used to transmit downlink beams back to the earth, or to another satellite in the case of an inter-satellite link, are not shown in FIG. 1 (or the rest of the figures in this application) for clarity. These elements include remodulation or digital remultiplexing circuitry, upconversion mixers for converting the processed baseband signals to an appropriate downlink frequency, high power amplifiers (HPA) for boosting the power of the upconverted signal, multiplexing where required, and the multiple spot-beam transmit antennas. Also not explicitly shown is the digital switch that is generally connected between the outputs of the digital processors and the downlink circuitry.
In the one-to-one system of FIG. 1, N digital processors are required. Each digital processor must be capable of handling the full-bandwidth (up to 125 MHz in the recently proposed systems) of an incoming uplink beam in order to provide flexibility for changing traffic patterns. Presently available space-qualified low-power digital technology cannot handle this bandwidth.
In reality, many of the uplink beams will have unoccupied spectrum and hence be underutilized, although some of the beams may be fully utilized. For example, an uplink beam from a heavily populated urban area may be fully utilized, some or all of the time, whereas a beam emanating from a rural area may only be partially used. The solution of FIG. 1 is inflexible and wastes a tremendous amount of processing power since there is no mechanism for allowing underutilized digital processors to assist with the processing of beams that contain a larger bandwidth of information. This system thus suffers from poor digital processor utilization, and requires the use of high-risk, non-proven digital processor technology.
Therefore, there remains a general need in the art of communication satellites for a digital satellite repeater that optimally uses available digital processing power. Moreover, there remains a need for such a digital satellite repeater that can be reconfigured in response to changes in the traffic pattern utilization of the satellite. In addition, there remains a need for such a digital satellite repeater that uses low-power, space-qualified processor technology.
More specifically, there remains a need for a digital satellite repeater that includes an analog pre-processor for switching, extracting and routing sub-bands of incoming uplink beams in order to optimize available on-board digital processing capabilities. There remains a further need for such an analog pre-processor that has the capability to adapt to changes in the traffic pattern by changing the way it switches and routes incoming beams, and by changing the portion (sub-band) of the incoming beam bandwidth that is extracted.
Yet another unfulfilled need in this art is for a digital satellite repeater that has an architecture which can provide for implementation of any kind of redundancy scheme, at minimal hardware cost. Such a repeater could easily accommodate standard 2:1 or 3:2 types of redundancy, as well as unconventional schemes such as 10:8 or 12:8. These unconventional schemes, such as 12:8, have higher reliability than, for example, four 3:2 conventional redundancy blocks, even though the amount of hardware is the same.
The present invention overcomes the problems noted above and satisfies the needs in this field for a digital satellite repeater that incorporates an analog pre-processor for switching, extracting and routing sub-bands from a plurality of incoming beams to a plurality of digital baseband processors.
The present invention provides an analog processor for use with digital satellite repeaters. The analog processor is connected between the receiving circuitry of the satellite and the on-board digital processors, and includes a switching matrix and a plurality of sub-band downconversion processing chains. Each sub-band processing chain includes a programmable frequency translator and bandpass filter which, in combination, extract or segment a portion of the total bandwidth of an incoming beam into sub-bands that may have differing bandwidths, and which route the sub-bands to a digital processor where the analog signal is converted to digital and processed.
The analog processor enables the digital processing power of the satellite to be optimized to the incoming traffic pattern of the uplink beams. If a certain beam is underutilized, then only spectral segments containing signals are extracted and routed for digital processing. The unused portion of the incoming beam is not processed.
Some of the sub-band segments may only be partially occupied if the bandpass filter bandwidths do not fit evenly into the utilized spectrum (e.g. in a 125 MHz beam, if 40 MHz is occupied and the sub-band processing chains have 25 MHz bandpass filters, then 2 sub-band processing chains are required for the beam, resulting in a full 25 MHz segment from one filter and a partially occupied 15 MHz segment from the second filter). Although in this case there is 10 MHz of wasted digital processing power (assuming 25 MHz digital processors), the design tradeoff is between optimum digital processing and extra filters required for increased bandwidth granularity (i.e. more filters with smaller bandwidths).
Instead of a one-to-one correspondence between beams and processors, the analog processor provides for a programmable one-to-K correspondence, where K could be one for underutilized beams, but in general will be greater than one for partially or fully utilized uplink beams. For example, if a given uplink beam is fully utilized at 125 MHz, and the satellite includes a plurality of 25 MHz digital processors, then the analog processor is programmed to switch the uplink beam to 5 sub-band processing chains, and segments and routes the five 25 MHz sub-bands for digital processing. If the traffic pattern on this beam is then changed for some reason such that only 75 MHz of information was being transmitted, the analog processor could be reprogrammed to switch the beam to only 3 sub-band processing chains. In this manner, the present invention is adaptable to changing traffic patterns, thus providing for continued optimization of the on-board digital processing power over the life of the satellite. This is a major advantage of the present invention over conventional digital processing repeaters.
Using the analog pre-processor of the present invention, a xe2x80x9cpoolxe2x80x9d of digital processors can be shared among multiple uplink beams, shifting the processing power among the beams as required by shifting beam utilization or traffic patterns. An additional advantage of the disclosed architecture is that any type of redundancy scheme can be implemented by simply adding downconversion or sub-band processing chains and reprogramming the included switching matrix to route the incoming beam to the appropriate redundant chain(s). The analog processor also enables the use of lower-power, proven digital processing technology.
As will be appreciated, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respect, all without departing from the invention. Accordingly, the drawings and description of the preferred embodiments are to be regarded as illustrative in nature and not restrictive.